1. Field of the Invention
The present invention relates to a digital delay unit, and more particularly, it relates to a digital delay unit for processing, e.g., video signals in a digital television receiver.
2. Description of the Prior Art
Generally employed as a mass storage digital delay means is the so-called digital delay unit for sequentially writing/reading signals in/from memory cells arrayed in the form of a matrix to arbitrarily delay the signals. FIG. 1 is a block diagram showing an example of a conventional digital delay unit. In FIG. 1, an input terminal 1 receives basic clock pulses .phi..sub.S. The unit delay (minimum delay width) in the digital delay unit is equal to one cycle of the basic clock pulses .phi..sub.S. The basic clock pulses .phi..sub.S inputted from the input terminal 1 are supplied to an address counter 2. The address counter 2 is incremented on the leading edges of the basic clock pulses .phi..sub.S, to output X addresses to an X decoder 3 and Y addresses to a Y decoder 4. Outputs from the X decoder 3 are supplied to a memory cell array 5 while those from the Y decoder 4 are supplied to a transfer gate 6.
On the other hand, input terminals 13.sub.1 to 13.sub.n are adapted to receive input data synchronously inputted with the basic clock pulses .phi..sub.S, and are described herein in structure for receiving n-bit input data. The most significant bit (MSB) of the input data is supplied to the terminal 13.sub.1 while the least significant bit (LSB) is supplied to the terminal 13.sub.n. The inupt data are supplied to a write circuit 10 which is controlled by signals WE through an input latch 11. The memory cell array 5 is formed by a group of memory cells arrayed in the form of a matrix, and the storage capacity thereof is M.times.n bits. The transfer gate 6 transfers data read from the memory cell array 5 to a sense amplifier 7 while transferring data from the write circuit 10 to the memory cell array 5. The sense amplifier 7 is controlled by signals SE to amplify the read data. A data latch 8 temporarily stores outputs from the sense amplifier 7. During a period of time when the signals SE are at low levels, the data latch 8 is electrically cut off from the sense amplifier 7. An output latch 9 generates delayed outputs from the data latch 8 in the cycle of the basic clock pulses .phi..sub.S, to supply the same to output terminals 12.sub.1 to 12.sub.n. The MSB of the output data is outputted from the terminal 12.sub.1 while the LSB is outputted from the terminal 12.sub.n.
The basic clock pulses .phi..sub.S received through the input terminal 1 are further supplied to a timing generator 14, which in turn generates the aforementioned signals SE and WE in such timing sequence as shown in FIG. 2. The signals SE are adapted to drive the sense amplifier 7 in high-level periods thereof while the signals WE are adapted to drive the write circuit 10 in high-level periods thereof. The address counter 2 is reset per M cycles by a reset circuit (not shown). The conventional digital delay unit is in the aforementioned structure.
The PAL system television receiver, implemented by the structure as shown in FIG. 1 is a one-line memory for sampling analog video signals at the frequency of 4 f.sub.sc (f.sub.sc : chrominance subcarrier frequency) to generate digital video signals and delay the same by one scanning line (lH) on the following conditions: M=1135, n=8, X addresses=X.sub.0 to X.sub.7, Y addresses=Y.sub.0 to Y.sub.2, and one cycle of the basic clock pulses .phi..sub.S is equal to 56 ns.
Operation of the conventional digital delay unit as shown in FIG. 1 is now described with reference to a timing chart as shown in FIG. 2. In this case, delay of M cycles is obtained by an M.times.n-bit memory having an address space for addresses A.sub.1 to A.sub.M for processing n-bit data in a parallel manner. The memory cell array 5 employed in this digital delay unit is formed by n memory cell groups having M-bit address capacity, and one memory cell in each group corresponds to one address. Therefore, when an address is designated, n memory cells in total are accessed from the n memory cell groups in a parallel manner. In a memory of the so-called byte structure, the number n is equal to 8. In the following description, symbols D.sub.1 to D.sub.M indicate input data newly stored in the addresses A.sub.1 to A.sub.M respectively and symbols PD.sub.1 to PD.sub.M indicate output data read from the addresses A.sub.1 to A.sub.M respectively.
First, the address counter 2 is driven by the basic clock pulses .phi..sub.S to supply X addresses to the X decoder 3 and Y addresses to the Y decoder 4. Then outputted to an I/O line 17 are data of n-bit memory cells in total belonging to columns coupled to the transfer gate 6 selected by the Y decoder 4 within the memory cells belonging to rows selected by the X decoder 3 in the memory cell array 5. For example, when the address A.sub.1 is designated by the output from the address counter 2, data PD.sub.1 on n memory cells in total positioned in respective addresses A.sub.1 of the n memory cell groups are read in parallel through the transfer gate 6. The n-bit data PD.sub.1 thus read are amplified by the sense amplifier 7 in a high-level period of the signal SE, to be fetched in the data latch 8. The data latch 8 is electrically cut off from the sense amplifier 7 on the trailing edge of the signal SE, thereby to hold the read data PD.sub.1 for the low-level period of the signal SE. The read data PD.sub.1 are transferred to the output latch 9, to be outputted from the n output terminals 12.sub.1 to 12.sub.n in a parallel manner. Thus, the data are sequentially read in correspondence to change of the address signals per one cycle of the basic clock pulses .phi..sub.S as shown in FIG. 2.
In the same address designating period after the fall of the signal SE, the write circuit 10 is driven in a high-level period of the signal WE to transfer n-bit input data received from an input latch 11 to the I/O line 17 to reload the data on the currently selected memory cells. For example, immediately after the preceding data PD.sub.1 are read from the address A.sub.1 to be stored in the data latch 8, new data D.sub.1 are written in the memory cells of the address A.sub.1. The data D.sub.l are read when the address A.sub.1 is again designated after M cycles. Thus, read-modified-write operation is performed every M cycles for the memory cells of the respective addresses so that newly written data are outputted after M cycles, thereby to obtain delay of M cycles.
In the conventional digital delay unit, read/write operation must be performed within one cycle of the basic clock pulses .phi..sub.S as hereinabove described. Therefore, the cycle of the basic clock pulses .phi..sub.S must be determined in consideration of read access time to data latch, writing completion time (pulse width of the signals WE), pulse width of the signals SE, timing margins between the address signals and the like, and it has been difficult to attain high-speed operation. For example, a cycle time of 56 ns is required for a digital delay unit applied to a PAL system television receiver, and if the aforementioned structure is employed in conventional process technique, the read-modified-write operation must be performed within the period of 56 ns. Thus, it has been difficult to drive the digital delay unit with sufficient timing margins.
An example of the aforementioned type prior art is disclosed in, e.g., "Television Gakkaishi (The journal of the institute of television engineers of Japan)" Vol. 39, No. 3 (1985) pp. 250 to 252. In this prior art literature, examples as shown in FIGS. 6 and 7 are at low speeds while an example as shown in FIG. 8 is at a high speed whereas the memory capacity is doubled, leading to increase in cost.